{"id":18751,"date":"2025-09-29T12:24:23","date_gmt":"2025-09-29T12:24:23","guid":{"rendered":"https:\/\/greencode.ge\/?post_type=product&p=18751"},"modified":"2025-09-29T12:24:23","modified_gmt":"2025-09-29T12:24:23","slug":"c6880-x-datasheet","status":"publish","type":"product","link":"https:\/\/greencode.ge\/en\/product\/c6880-x-datasheet\/","title":{"rendered":"C6880-X Datasheet"},"content":{"rendered":"

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C6880-X Datasheet Specification<\/strong><\/h3>\n<\/td>\n<\/tr>\n

\n

QoS Features and Scalability<\/strong><\/p>\n<\/td>\n<\/tr>\n

Feature<\/td>\nC6880-X Datasheet<\/td>\n<\/tr>\n
Layer-3 classification and marking access control entries (ACEs)<\/td>\n256K shared for QoS\/Security<\/td>\n<\/tr>\n
Aggregate traffic rate-limiting policers<\/td>\n16,348<\/td>\n<\/tr>\n
Flow-based rate-limiting method; number of rates<\/td>\nPer source address, destination address, or full flow; 64 rates<\/td>\n<\/tr>\n
Layer 2 rate limiters<\/td>\n20 ingress\/6 egress<\/td>\n<\/tr>\n
MAC ACLs featuring per-port\/per VLAN granularity<\/td>\nYes<\/td>\n<\/tr>\n
Distributed policers<\/td>\nYes<\/td>\n<\/tr>\n
Shared uFlow policers<\/td>\nYes<\/td>\n<\/tr>\n
Egress uFlow policers<\/td>\nYes<\/td>\n<\/tr>\n
Packet or byte policers<\/td>\nYes<\/td>\n<\/tr>\n
Per port per VLAN<\/td>\nYes<\/td>\n<\/tr>\n
COS and DSCP based Queue mapping<\/td>\nYes<\/td>\n<\/tr>\n
Deficit Weighted Round Robin Scheduler (DWRR) and Weighted Random Early Detection Scheduler (WRED)<\/td>\nYes<\/td>\n<\/tr>\n
Receive and Transmit Queues<\/td>\nDefault: 1p7q4t<\/p>\n

Configurable: 2p6q4t<\/td>\n<\/tr>\n

\n

Security Features and Scalability<\/strong><\/p>\n<\/td>\n<\/tr>\n

Port security<\/td>\nYes<\/td>\n<\/tr>\n
IEEE 802.1x and 802.1x extensions<\/td>\nYes<\/td>\n<\/tr>\n
VLAN and router ACLs and port ACLs<\/td>\nYes<\/td>\n<\/tr>\n
1:1 mask ratio to ACE values<\/td>\nYes<\/td>\n<\/tr>\n
Security ACL entries<\/td>\n256K shared for QoS\/Security<\/td>\n<\/tr>\n
CPU rate limiters (DoS protection)<\/td>\n57<\/td>\n<\/tr>\n
uRPF check (IPv4\/IPv6)<\/td>\nUp to 16<\/td>\n<\/tr>\n
Number of interfaces with unique ACL<\/td>\n16k<\/td>\n<\/tr>\n
RPF interfaces<\/td>\n16<\/td>\n<\/tr>\n
Private VLANs<\/td>\nYes<\/td>\n<\/tr>\n
MAC ACLs on IP<\/td>\nYes<\/td>\n<\/tr>\n
Layer 2 and Layer 3 Cisco TrustSec<\/p>\n

(Security Group Tagging & Security Group Access Control List)<\/td>\n

Yes<\/td>\n<\/tr>\n
IEEE 802.1ae (MACsec) Layer 2 encryption in hardware<\/td>\nYes<\/td>\n<\/tr>\n
CPU HW rate limiters by PPS or BPS<\/td>\nYes<\/td>\n<\/tr>\n
CoPP for multicast<\/td>\nL2 and L3 support<\/td>\n<\/tr>\n
CoPP for exceptions (MTU, TTL)<\/td>\nYes<\/td>\n<\/tr>\n
CoPP exceptions NetFlow support<\/td>\nYes<\/td>\n<\/tr>\n
ACL labels<\/td>\n16K<\/td>\n<\/tr>\n
Port ACL<\/td>\n8K<\/td>\n<\/tr>\n
ACL dry run<\/td>\nYes<\/td>\n<\/tr>\n
Hitless ACL changes<\/td>\nYes<\/td>\n<\/tr>\n
\n

MPLS and Virtualization Features<\/strong><\/p>\n<\/td>\n<\/tr>\n

VSS*<\/td>\nYes<\/td>\n<\/tr>\n
Label imposition\/disposition (MPLS-PE), swapping (MPLS\u2011P)<\/td>\nYes<\/td>\n<\/tr>\n
Label Distribution Protocol (LDP)<\/td>\nYes<\/td>\n<\/tr>\n
MPLS VPN<\/td>\nYes<\/td>\n<\/tr>\n
VRF Lite<\/td>\nYes<\/td>\n<\/tr>\n
EVN<\/td>\nYes<\/td>\n<\/tr>\n
QoS mechanisms using experimental (EXP) bits<\/td>\nYes<\/td>\n<\/tr>\n
MPLS-RSVP-TE<\/td>\nYes<\/td>\n<\/tr>\n
MPLS differentiated services (diffserv)-aware traffic engineering (MPLS-DS-TE)<\/td>\nYes<\/td>\n<\/tr>\n
MPLS traceroute<\/td>\nYes<\/td>\n<\/tr>\n
EoMPLS<\/td>\nYes<\/td>\n<\/tr>\n
EoMPLS tunnels<\/td>\n16k<\/td>\n<\/tr>\n
IPv4 and IPv6 in IPv6 tunneling<\/td>\nYes<\/td>\n<\/tr>\n
IPv6 in IPv4 tunnelling (Intra-Site Automatic Tunnel Addressing Protocol [ISATAP], 6to4, GRE<\/td>\nYes<\/td>\n<\/tr>\n
QoS support for uniform, short pipe and pipe mode tunnel<\/td>\nYes<\/td>\n<\/tr>\n
Native VPLS in HW<\/td>\nYes<\/td>\n<\/tr>\n
Native L2 over multipoint GRE<\/td>\nYes<\/td>\n<\/tr>\n
VRF-aware operational contexts<\/td>\nYes<\/td>\n<\/tr>\n
VPN NetFlow support<\/td>\nYes<\/td>\n<\/tr>\n
VPN aware NAT<\/td>\nYes<\/td>\n<\/tr>\n
VRF-lite scalability<\/td>\nVLAN reuse per subinterface<\/td>\n<\/tr>\n
Per VPN interface statistics<\/td>\nYes<\/td>\n<\/tr>\n
\n

Netflow and Multicast Features<\/strong><\/p>\n<\/td>\n<\/tr>\n

Netflow support in hardware<\/td>\nYes<\/td>\n<\/tr>\n
Flexible Netflow<\/td>\nYes<\/td>\n<\/tr>\n
Sampled Netflow<\/td>\nYes<\/td>\n<\/tr>\n
Ingress\/Egress Netflow<\/td>\nYes<\/td>\n<\/tr>\n
Ingress and Egress replication in hardware<\/td>\nYes<\/td>\n<\/tr>\n
IGMPv3 snooping in hardware<\/td>\nYes<\/td>\n<\/tr>\n
IPv6 MLDv2 snooping in hardware<\/td>\nYes<\/td>\n<\/tr>\n
PIM registers in hardware<\/td>\nYes<\/td>\n<\/tr>\n
Label Switched Multicast (LSM)<\/td>\nYes<\/td>\n<\/tr>\n
\n

Base System Scalability<\/strong><\/p>\n<\/td>\n<\/tr>\n

MAC entries<\/td>\n128K<\/td>\n<\/tr>\n
Routes<\/td>\n2048K (IPv4)<\/p>\n

1024K (IPv6)<\/td>\n<\/tr>\n

ACL entries<\/td>\n256K shared for QoS\/Security<\/td>\n<\/tr>\n
NetFlow entries<\/td>\n1024K (per module slot)<\/p>\n

Up to 5M per system<\/td>\n<\/tr>\n

Multicast routes<\/td>\n128K (IPv4)<\/p>\n

128K (IPv6)<\/td>\n<\/tr>\n

IPv4 routing<\/td>\nIn hardware<\/p>\n

Up to 300 Mpps**<\/td>\n<\/tr>\n

IPv6 routing<\/td>\nIn hardware<\/p>\n

Up to 150 Mpps**<\/td>\n<\/tr>\n

L2 bridging<\/td>\nIn hardware<\/p>\n

Up to 300 Mpps**<\/td>\n<\/tr>\n

Jumbo frame support<\/td>\nUp to 9216 bytes<\/p>\n

(For bridged and routed pkts.)<\/td>\n<\/tr>\n

VLAN<\/td>\n4K<\/td>\n<\/tr>\n
Bridge domains<\/td>\n16K<\/td>\n<\/tr>\n
MPLS<\/td>\nIn hardware (up to 8192 VRFs at 300 Mpps**)<\/td>\n<\/tr>\n
Logical interfaces<\/td>\n128K<\/td>\n<\/tr>\n
EtherChannel hash<\/td>\n8 bits<\/td>\n<\/tr>\n
VPLS<\/td>\nIn hardware (up to 150 Mpps**)<\/td>\n<\/tr>\n
GRE<\/td>\nIn hardware (up to 150 Mpps**)<\/td>\n<\/tr>\n
NAT<\/td>\nHardware assisted<\/td>\n<\/tr>\n
Onboard memory<\/td>\n4GB<\/td>\n<\/tr>\n
Ingress buffers<\/td>\n1.25MB per 10G port in 2:1 mode<\/p>\n

2.5MB per 10G port in 1:1 mode<\/p>\n

(10MB per Port ASIC)<\/td>\n<\/tr>\n

Egress buffers<\/td>\n24MB per 10G port in 2:1 mode<\/p>\n

48MB per 10G port in 1:1 mode<\/p>\n

(192MB per MUX FPGA)<\/td>\n<\/tr>\n

\n

Software Packaging<\/strong><\/p>\n<\/td>\n<\/tr>\n

Software License<\/td>\n\u25cf\u00a0\u00a0IP Services<\/p>\n

\u25cf\u00a0\u00a0Advanced Enterprise Services<\/td>\n<\/tr>\n

Software compatibility<\/td>\n15.1(2)SY1 and later releases*<\/td>\n<\/tr>\n<\/tbody>\n<\/table>","protected":false},"excerpt":{"rendered":"\n\n\n\n
Model:<\/td>\nCisco Catalyst Switch C6880-X Datasheet Chassis with fixed configuration<\/td>\n<\/tr>\n
Detail:<\/td>\nCisco Catalyst 6800 switch chassis, 5RU, Super 2TXL Engine, no PS, no Fan Tray<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

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